1. Technical Field
The present disclosure relates in general to a circuit for power management of standard cell application. In particular, the present disclosure relates to a circuit for power management of standard cell application using a head switch and a latch.
2. Description of the Related Art
Standby leakage problems, occurring when a chip is in standby mode, are serious concerns in very deep submicron technology with device size reductions. FIG. 1 shows current leakage sources in a transistor 10. The transistor 10 comprises a gate 12, a source 14, a drain 16 and a well 18. Current leakage is caused by junction leakage I1, weak inversion I2, drain induced barrier lowering I3, gate induced drain leakage I4, punchthrough I5, narrow width effect I6, gate oxide tunneling I7 and hot carrier injection I8.
The increased subthreshold leakage and gate leakage current not only increase the IC reliability issues, but also increase the package cost in order to handle the excess power dissipation. The rapidly increased leakage current leads the huge power consumption when the IC chip is getting bigger, taster and denser. Power management technique becomes the required design issue. Recently, there were several patents declared to handle the huge power consumption problems. However, they are all existed some design issues and limitations.
U.S. Pat. No. 6,287,920 to Chatterjee, et al. discloses a method for forming multiple threshold voltage integrated into circuit transistors. Angled pocket type implants are formed to create asymmetric regions. The source and drain regions are connected such that multiple threshold voltage transistors are formed. Several different threshold voltage libraries must be employed to implement the multiple threshold voltage method. In addition, power saving is typically limited and often insufficient. The multiple threshold voltage method requires extra masks for different threshold voltage and power.
U.S. Pat. No. 6,664,608 to Burr, et al. discloses a back-biased MOS device. Both of p-wells and n-wells are formed on a front side of a bulk material. The N devices and P devices are formed respectively within the P-wells or N-wells. The P-wells or N-wells are electrically isolated from one another and are routed to the different potentials to vary their threshold voltages. The changed threshold voltages will than be used to reduce their subthreshold leakage currents.
However, disadvantages of the back-biased method include the need for additional charge pumps or multiple power supplies to apply extra bias to the well and/or substrate, the junction or gate oxide breakdown concerns, the excessive time required to charge or discharge between different modes, the required deep N-well process, and the design complexity.
U.S. Pat. No. 6,667,648 to Stout, et al. discloses a voltage island communications circuit. An integrated circuit comprises a first circuit powered by a first power supply. The first circuit sends a first signal referenced to the voltage of the first power supply to a second circuit powered by a second power supply. The second circuit receives the first signal and converts the first signal to a second signal of the same logical value as the first signal and is referenced to the voltage of the second power supply. However, complicated design and complex tools are required by the voltage island method. In addition, the voltage island method cannot solve leakage problems in most active circuit blocks.
The multiple Vt method needs multiple standard cell libraries and cannot save enough power when the chip has so many critical paths. The back-biased MOS method has the junction breakdown and gate oxide breakdown concerns and has the limited power saving in the very deep submicron technology. The very deep submicron technology has the less efficient threshold voltage variation by using the backed-gate bias. Both of those methods cannot solve the gate leakage problem which because major concern in the 90 nm technology and beyond. The voltage island method, however, needs the complexity of software and hardware interaction which tends to increase the design difficulty.